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ADV7195
MODE REGISTER 1
MR1 (MR17–MR10)
(Address (SR4-SR0) = 01H)
Figure 51 shows the various operations under the control of
Mode Register 1.
MR1 BIT DESCRIPTION
Pixel Data Enable (MR10)
When this bit is set to “0,” the pixel data input to the ADV7195
is blanked such that a black screen is output from the DACs.
When this bit is set to “1,” pixel data is accepted at the input
pins and the ADV7195 outputs to the standard set in “Output
Standard Selection” (MR01–00). This bit also must be set to
“1” to enable output of the test pattern signals.
Input Format (MR11)
It is possible to input data in 4:2:2 format or in 4:4:4
HDTV format.
Test Pattern Enable (MR12)
Enables or disables the internal test pattern generator.
Test Pattern Hatch/Frame (MR13)
If this bit is set to “0,” a crosshatch test pattern is output from
the ADV7195. The crosshatch test pattern can be used to test
monitor convergence.
If this bit is set to “1,” a uniform colored frame/field test pattern
is output from the ADV7195.
The color of the lines or the frame/field is white by default but
can be programmed to be any color using the Color Y, Color
Cr, Color Cb registers.
VBI Open (MR14)
This bit enables or disables the facility of VBI data insertion
during the Vertical Blanking Interval.
For this purpose Lines 7–20 in 1080i and Lines 6–25 in 720p
can be used for VBI data insertion.
Reserved (MR15–MR17)
A “0” must be written to these bits.
MR07
MR06
MR05
MR04
MR03
MR02
MR01
MR00
MR07
ZERO MUST
BE WRITTEN
INPUT
STANDARD
MR05
MR04
ZERO MUST
BE WRITTEN
INPUT CONTROL SIGNALS
MR03 MR02
TO THIS BIT
0
1
1080I
720P
TO THIS BIT
0
0
0
1
HSYNC / VSYNC /DV
EAV/SAV
DV POLARITY
1
1
0
1
TSYNC/ SYNC /DV
RESERVED
MR06
0 ACTIVE HIGH
OUTPUT STANDARD SELECTION
MR01 MR00
1 ACTIVE LOW
0
0
1
1
0
1
0
1
EIA770.3
RESERVED
FULL I/P RANGE
RESERVED
Figure 50. Mode Register 0
MR17
MR16
MR15
MR14
MR13
MR12
MR11
MR10
MR17 – MR15
ZERO MUST
BE WRITTEN
TO THIS BIT
VBI OPEN
MR14
0 DISABLE
1 ENABLE
TEST PATTERN
ENABLE
MR12
0 DISABLE
1 ENABLE
PIXEL DATA
ENABLE
MR10
0 DISABLE
1 ENABLE
TEST PATTERN
HATCH/FRAME
MR13
0 HATCH
1 FIELD/FRAME
Figure 51. Mode Register 1
INPUT FORMAT
MR11
0 4:4:4 Y CR CB
1 4:2:2 Y CR CB
REV. A
–27 –
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